The present invention relates to systems and methods for an intermediate representation of a custom integrated circuit (IC) or an application-specific integrated circuit (ASIC).
As electronics become more user friendly, the features imposed on the electronics have grown. For example, in a typical hardware product development cycle for an embedded application, algorithm development is done. Next, system architects break down how the algorithms need to be implemented in the product. Conventionally, the algorithm is converted into a low level intermediate representation such as a register transfer language (RTL) that is close to the hardware.
RTL is commonly used in the electronics design industry to refer to the coding style used in hardware description languages that effectively guarantees the code model can be synthesized (converted to real logic functions) in a given hardware platform such as an FPGA or an ASIC.
There are many hardware description languages that can be used to create RTL modules for logic synthesis. Some of the most popular RTL modeling languages include: System Verilog, Verilog, and VHDL.
United States Patent Application 20090144690 discloses a method for converting a C-type programming language program to a hardware design, where the program is an algorithmic representation of one or more processes. The C-type programming language program is compiled into a hardware description language (HDL) synthesizable design. The compiler categorizes variables as using either implicit memory or custom memory. The programming language may use ANSI C and the HDL may be Verilog Register Transfer Level (RTL). The hardware device generated from the HDL synthesizable design may be an Application-Specific Integrated Circuit (ASIC) or a Field Programmable Gate Array (FPGA).
However, RTL is still a low level description of the hardware. Thus, it can be difficult to analyze and subsequently to optimize a design with RTL.